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never stop thinking. hyb25d512400at hyb25d512800at hyb25d512160at 512mbit double data rate sdram ddr sdram data sheet, rev. 1.0, march 2004 memory products
the information in this document is subject to change without notice. edition 2004-03 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb25d512400at hyb25d512800at hyb25d512160at 512mbit double data rate sdram ddr sdram data sheet, rev. 1.0, march 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hyb25d512400at hyb25d512800at hyb25d512160at revision history: rev. 1.0 2004-03 previous revision: rev. 0.92 2004-02 all editorial changes see change list previous revision: rev. 0.91 2003-08 page subjects (major changes since last revision) all deleted ?5 and ?8 speed we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.4 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.1 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.2 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.3 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.4 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.5 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.6 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 normal strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 weak strength pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.5 i dd1 : operating current: one bank operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table of contents
hyb25d512[16/40/80]0at?[6/7/7f] overview data sheet 6 rev. 1.0, 2004-03 1 overview 1.1 features double data rate architecture: two data transfers per clock cycle bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver dqs is edge-aligned with data for reads and is center-aligned with data for writes differential clock inputs (ck and ck ) four internal banks for concurrent operation data mask (dm) for write data dll aligns dq and dqs transitions with ck transitions commands entered on each positive ck edge; data and data mask referenced to both edges of dqs burst lengths: 2, 4, or 8 cas latency: (1.5), 2, 2.5, 3 auto precharge option for each burst access auto refresh and self refresh modes 7.8 s maximum average periodic refresh interval 2.5 v (sstl_2 compatible) i/o v ddq = 2.5 v 0.2 v (ddr266a, ddr333) v dd = 2.5 v 0.2 v (ddr266, ddr333) p-tsop66ii-1 package 1.2 description the 512mbit double data rate sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512mbit double data rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mbit double data rate sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 512mbit double data rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration table 1 performance ?6/?7/?7f part number speed code ? 6?7-7funit speed grade component ddr333b ddr266a ddr266 ? module pc2700?2533 pc2100-2033 pc2100-2022 ? max. clock frequency @cl3 f ck3 166 ? ? mhz @cl2.5 f ck2.5 166 143 143 mhz @cl2 f ck2 133 133 133 mhz
data sheet 7 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] overview of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. table 2 ordering information part number 1) 1) hyb: designator for memory components; 25d: ddr sdrams at v ddq = 2.5 v; 512: 512mbit density; 400/800/160: product variations x4, x8 and x16: a: die revision a; t: package type tsop; ?6/?7/?7f: speed grade - see table 2 org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package hyb25d512400at?6 4 2.5-3-3 166 2.0-3-3 133 ddr333 p-tsop66ii-1 hyb25d512800at?6 8 hyb25d512160at?6 16 hyb25d512400at?7 4143 ddr266a hyb25d512800at?7 8 hyb25d512160at?7 16 hyb25d512800at?7f 8 2.0-2-2 ddr266
hyb25d512[16/40/80]0at?[6/7/7f] pin configuration data sheet 8 rev. 1.0, 2004-03 2 pin configuration figure 1 pin configuration p-tsop66ii-1 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq n.c. dq1 v ssq v ddq n.c. dq3 v ssq n.c. n.c. n.c. dq2 v ddq n.c. n.c. v dd n.c. n.c. we cas ras cs n.c. ba0 ba1 v ss dq7 v ssq n.c. dq6 v ddq v ssq n.c. dq4 v ddq n.c. n.c. n.c. dq5 v ssq dqs n.c. v ref v ss dm ck ck cke n.c. a12 a11 a9 v dd n.c. v ddq n.c. dq0 v ssq v ddq n.c. dq1 v ssq n.c. n.c. n.c. n.c. v ddq n.c. n.c. v dd n.c. n.c. we cas ras cs n.c. ba0 ba1 v ss n.c. v ssq n.c. dq3 v ddq v ssq n.c. dq2 v ddq n.c. n.c. n.c. n.c. v ssq dqs n.c. v ref v ss dm ck ck cke n.c. a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss 128mb x 4 64mb x 8 v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 n.c. dq3 dq4 v ddq ldqs n.c. v dd n.c. ldm we cas ras cs n.c. ba0 ba1 a10/ap a0 a1 a2 a3 v dd 32mb x 16 v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 n.c. dq12 dq11 v ssq udqs n.c. v ref v ss udm ck ck cke n.c. a12 a11 a9 a8 a7 a6 a5 a4 v ss
data sheet 9 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] pin configuration table 3 input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ldm and udm are the input mask signals for 16 components and control the lower or upper bytes. for 8 components the data mask function is disabled, when rdqs / rqds are enabled by emrs(1) command. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 - a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input/ output data input/output: data bus. dqs, (dqs ) ldqs, (ldqs ), udqs,(udqs ) input/ output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the 16, ldqs corresponds to the data on ldq[0:7]; udqs corresponds to the data on udq[0:7]. the data strobes dqs, ldqs, udqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals. n.c. ? no connect: no internal electrical connection is present. v ddq supply dq power supply: 2.5 v 0.2 v. v ssq supply dq ground v dd supply power supply: 2.5 v 0.2 v. v ss supply ground v ref supply sstl_2 reference voltage: ( v ddq /2)
hyb25d512[16/40/80]0at?[6/7/7f] pin configuration data sheet 10 rev. 1.0, 2004-03 figure 2 block diagram 128 mbit 4 note: 1. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. spb04304 control logic row-address mux 8192 bank0 row-address latch & decoder bank control logic column decoder column decoder column decoder i/o gating dm mask logic 16384 sense amplifier bank0 memory array (8192 x 2048 x 8) bank1 2048 (x8) refresh counter 13 2 column decoder 2 column-address counter/latch 11 1 col0 address register 12 13 15 mode registers command decode ras cas we cs ck ck cke a0 - a12, ba0, ba1 8 1 1 4 4 1 4 1 1 4 4 2 8 data mask write fifo & drivers 8 col0 ck, ck receivers input register mux col0 dqs generator drivers 4 1 data dqs 4 4 read latch 8 1 dll ck, ck dqs dq0- dq3, dm 15 13 bank2 bank3
data sheet 11 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] pin configuration figure 3 block diagram 64 mbit 8 note: 1. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. spb04305 control logic row-address mux 8192 bank0 row-address latch & decoder bank control logic column decoder column decoder column decoder i/o gating dm mask logic 16384 sense amplifier bank0 memory array (8192 x 1024 x 16) bank1 1024 (x16) refresh counter 13 2 column decoder 2 column-address counter/latch 10 1 col0 address register 11 13 15 mode registers command decode ras cas we cs ck ck cke a0 - a12, ba0, ba1 16 1 1 8 8 1 8 1 1 8 8 2 16 data mask write fifo & drivers 16 col0 ck, ck receivers input register mux col0 dqs generator drivers 8 1 data dqs 8 8 read latch 16 1 dll ck, ck dqs dq0- dq7, dm 15 13 bank2 bank3
hyb25d512[16/40/80]0at?[6/7/7f] pin configuration data sheet 12 rev. 1.0, 2004-03 figure 4 block diagram 32 mbit 16 note: 1. this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. udm and ldm are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional dq, udqs and ldqs signals. spb04306 control logic row-address mux 8192 bank0 row-address latch & decoder bank control logic column decoder column decoder column decoder i/o gating dm mask logic 16384 sense amplifier bank0 memory array (8192 x 512 x 32) bank1 512 (x32) refresh counter 13 2 column decoder 2 column-address counter/latch 9 1 col0 address register 10 13 15 mode registers command decode ras cas we cs ck ck cke a0 - a12, ba0, ba1 32 1 1 16 16 2 16 1 1 16 16 2 32 data mask write fifo & drivers 32 col0 ck, ck receivers input register mux col0 dqs generator drivers 16 1 data dqs 16 16 read latch 32 2 dll ck, ck ldqs, udqs dq0- dq15, ldm, udm 15 13 bank2 bank3
data sheet 13 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 3 functional description the 512mbit double data rate sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. the 512mbit double data rate sdram is internally configured as a quad-bank dram. the 512mbit double data rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mbit double data rate sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. 3.1 initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following criteria must be met: no power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output v tt meets the specification a minimum resistance of 42 ? limits the input current from the v tt supply into any pin and v ref tracks v ddq /2 or the following relationship must be followed: v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v v tt is driven after or with v ddq such that v tt < v ddq + 0.3 v v ref is driven after or with v ddq such that v ref < v ddq + 0.3 v the dq and dqs outputs are in the high-z state, where they remain until driven in normal operation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200 s delay prior to applying an executable command. once the 200 s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any executable command. during the 200 cycles of clock for dll locking, a deselect or nop command must be applied. after the 200 clock cycles, a precharge all command should be applied, placing the device in the ?all banks idle? state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation.
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 14 rev. 1.0, 2004-03 3.2 mode register definition the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4- a6 specify the cas latency, and a7-a12 specify the operating mode. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified operation. 3.2.1 burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. mr mode register definition (ba[1:0] = 00 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 0 mode cl bt bl reg. addr w w w w field bits type description bl [2:0] w 1) 1) w = write only register bit burst length number of sequential bits per dq related to one read/write command; see chapter 3.2.1 . note: all other bit combinations are reserved. 001 2 010 4 011 8 bt 3w 1) burst type see table 4 for internal address sequence of low order address bits; see chapter 3.2.2 . 0 sequential 1 interleaved cl [6:4] w 1) cas latency number of full clocks from read command to first data valid window; see chapter 3.2.3 . note: all other bit combinations are reserved. 010 2 011 3 101 (1.5 optional, not covered by this data sheet) 110 2.5 mode [12:7] w 1) operating mode see chapter 3.2.4 . note: all other bit combinations are reserved. 000000 normal operation 000010 dll reset
data sheet 15 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2-ai when the burst length is set to four and by a3-ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. 3.2.2 burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 4 . notes 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 3.2.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2, 2.5 and 3 clocks. cas latency of 1.5 is an optional feature on this device. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m .(see figure 5 ) reserved states should not be used as unknown operation or incompatibility with future versions may result. table 4 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 16 rev. 1.0, 2004-03 3.2.4 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a12 each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode (i.e., with a8=0). all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 5 required cas latencies nop nop nop nop nop read cas latency = 2, bl = 4 shown with nominal t ac , t dqsck , and t dqsq . ck ck command dqs dq don?t care cl=2 nop nop nop nop nop read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5
data sheet 17 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 3.3 extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, and output drive strength selection (optional). these functions are controlled via the bits shown in the extended mode register definition. the extended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. 3.3.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or write command upon exit of self refresh operation. 3.3.2 output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. in addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. i - v curves for the normal and weak drive strength are included in this document. emr extended mode register definition (ba[1:0] = 01 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 0 1 operating mode ds dll reg. addr w w w field bits type description dll 0w dll status see chapter 3.3.1 . 0 enabled 1 disabled ds 1w drive strength see chapter 3.3.2 , chapter 4.2 and chapter 4.3 . 0normal 1weak mode [12:2] w operating mode note: all other bit combinations are reserved. 00000000000 normal operation
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 18 rev. 1.0, 2004-03 3.4 commands deselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1. see mode register descriptions in chapter 3.2 . the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or write with auto precharge) is issued to that bank. a precharge (or read or write with auto precharge) command must be issued and completed before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 8, j = don?t care] for x16, [i = 9, j = don?t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the write command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, aj (where [i = 9, j = don?t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a write is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command is treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging.
data sheet 19 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge ( t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in chapter 3.5 . burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command is truncated, as shown in chapter 3.5 . auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 512mbit double data rate sdram requires auto refresh cycles at an average periodic interval of 7.8 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 7.8 s (70.2 s). this maximum absolute interval is short enough to allow for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with cke transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except cke (low) are ?don?t care? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to cke returning high. once cke is high, the sdram must have nop commands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for 200 clock cycles before applying any other command.
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 20 rev. 1.0, 2004-03 table 5 truth table 1a: commands name (function) cs ras cas we address mne notes deselect (nop) h x x x x nop 1)2) no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) read (select bank and column, and start read burst) l h l h bank/col read 1)4) write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate lhhlx bst 1)5) precharge (deactivate row in bank or banks) l l h l code pre 1)6) auto refresh or self refresh (enter self refresh mode) l l l h x ar/sr 1)7)8) mode register set l l l l op-code mrs 1)9) 1) cke is high for all commands shown except self refresh. 2) deselect and nop are functionally interchangeable. 3) ba0-ba1 provide bank address and a0-a12 provide row address. 4) ba0, ba1 provide bank address; a0-ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. 5) applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. 6) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. 7) this command is auto refresh if cke is high; self refresh if cke is low. 8) internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for cke. 9) ba0, ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register). table 6 truth table 1b: dm operation name (function) dm dqs notes write enable lvalid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx 1)
data sheet 21 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 3.5 operations 3.5.1 bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see figure 6 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . figure 6 activating a specific row in a specific bank figure 7 t rcd and t rrd definition ra ba high ra = row address. ba = bank address. ck ck cke cs ras cas we a0-a12 ba0, ba1 don?t care row act nop col row ba y ba y ba x act nop nop ck ck command a0-a12 ba0, ba1 don?t care rd/wr t rcd t rrd rd/wr nop nop
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 22 rev. 1.0, 2004-03 3.5.2 reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command, as shown on figure 8 . the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of ck and ck ). figure 9 shows general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs goes high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on figure 10 . a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is illustrated on figure 11 . full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on figure 12 . figure 8 read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck x16: a0-a8
data sheet 23 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 9 read burst: cas latencies (burst length = 4) cas latency = 2 nop nop nop nop nop read ck ck command address dqs dq cas latency = 2.5 don?t care ba a,col n doa-n cl=2.5 nop nop nop nop nop read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . cl=2
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 24 rev. 1.0, 2004-03 figure 10 consecutive read bursts: cas latencies (burst length = 4 or 8) cas latency = 2 nop read nop nop nop read ck ck command address dqs dq cl=2 baa, col n baa, col b don?t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). when burst length = 4, the bursts are concatenated. when burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shown with nominal t ac , t dqsck , and t dqsq . cas latency = 2.5 nop read nop nop nop read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b
data sheet 25 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 11 non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 nop nop read nop nop read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programm ed order following do a-n (and following do a-b). shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col b cl=2 cas latency = 2.5 nop nop read nop nop read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq nop
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 26 rev. 1.0, 2004-03 figure 12 random read accesses: cas latencies (burst length = 2, 4 or 8) data from any read burst may be truncated with a burst terminate command, as shown on figure 13 . the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs. data from any read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown on figure 14 . the example is shown for t dqss(min) . the t dqss(max) case, not shown here, has a longer bus idle time. t dqss(min) and t dqss(max) are defined in chapter 3.5.3 . a read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on figure 15 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data elements. doa-n cas latency = 2 read read read nop nop read doa-b doa-n? doa-x doa-x? doa-b? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac , t dqsck , and t dqsq . don?t care baa, col n baa, col x baa, col b baa, col g cl=2 cas latency = 2.5 read read read nop nop read ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5 doa-n doa-b doa-n? doa-x doa-x? doa-b?
data sheet 27 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 13 terminating a read burst: cas latencies (burst length = 8) cas latency = 2 nop bst nop nop nop read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . doa-n don?t care ck baa, col n cl=2 cas latency = 2.5 nop bst nop nop nop read ck command address dqs dq doa-n ck baa, col n cl=2.5 no further output data after this point. dqs tristated. no further output data after this point. dqs tristated.
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 28 rev. 1.0, 2004-03 figure 14 read to write: cas latencies (burst length = 4 or 8) cas latency = 2 bst nop write nop nop read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don?t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst nop nop write nop read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac , t dqsck , and t dqsq . . di a-b = data in to bank a, column b
data sheet 29 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 15 read to precharge: cas latencies (burst length = 4 or 8) cas latency = 2 nop pre nop nop act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac , t dqsck , and t dqsq . don?t care ba a, col n ba a or all ba a, row cl=2.5 cas latency = 2.5 nop pre nop nop act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, row cl=2 t rp
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 30 rev. 1.0, 2004-03 3.5.3 writes write bursts are initiated with a write command, as shown in figure 16 . the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is registered on the first rising edge of dqs following the write command, and subsequent data elements are registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss ) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the write diagrams that follow are drawn for the two extreme cases (i.e. t dqss(min) and t dqss(max) ). figure 17 shows the two extremes of t dqss for a burst of four. upon completion of a burst, assuming no other commands have been initiated, the dqs and dqs enters high-z and any additional input data is ignored. data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). figure 18 shows concatenated bursts of 4. an example of non-consecutive writes is shown in figure 19 . full-speed random write accesses within a page or pages can be performed as shown in figure 20 . data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr (write to read) should be met as shown in figure 21 . data for any write burst may be truncated by a subsequent read command, as shown in figure 22 to figure 24 . note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met as shown in figure 25 . data for any write burst may be truncated by a subsequent precharge command, as shown in figure 26 to figure 28 . note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a write burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
data sheet 31 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 16 write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca x4: a0-a9, a11 x8: a0-a9 x16: a0-a8 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 32 rev. 1.0, 2004-03 figure 17 write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) nop nop nop write di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the write comm and (auto precharge is disabled). ck ck command address dqs dq dm don?t care maximum dqss ba a, col b t1 t2 t3 t4 t dqss (min) nop nop nop write ck ck command address dqs minimum dqss ba a, col b dq dm dla-b dla-b
data sheet 33 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 18 write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop write nop nop nop write di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed or der following di a-b. 3 subsequent elements of data in are applied in the programmed or der following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care t1 t2 t3 t4 t5 t6 minimum dqss nop write nop nop nop write ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 34 rev. 1.0, 2004-03 figure 19 write to write: max. dqss, non-consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) nop nop write nop write di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. each write command may be to any bank. ck ck command address dqs dq dm don?t care baa, col b baa, col n di a-b di a-n
data sheet 35 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 20 random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum dqss write write write write write di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). each write command may be to any bank. di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm don?t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum dqss write write write write write di a-b di a-n di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 36 rev. 1.0, 2004-03 figure 21 write to read: non-interrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write di a-b nop di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wtr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write command (auto precharge is disabled). the read and write commands may be to any bank. ck ck command address dqs dq dm don?t care maximum dqss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t wtr nop nop nop read write nop ck ck command address minimum dqss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2
data sheet 37 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 22 write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). the read and write commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 t1 t2 t3 t4 t5 t6 minimum dqss nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 38 rev. 1.0, 2004-03 figure 23 write to read: minimum dqss, odd number of data (3-bit write), interrupting (cas latency = 2; burst length = 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto prechar ge is disabled). the read and write commands are not necessarily to the same bank. don?t care t1 t2 t3 t4 t5 t6 nop nop nop read write nop ck ck command address baa, col b baa, col n t wtr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low.
data sheet 39 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 24 write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) nop nop nop read write nop di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t wtr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the write comm and (auto prechar ge is disabled). the read and write commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don?t care baa, col b baa, col n t wtr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 40 rev. 1.0, 2004-03 figure 25 write to precharge: non-interrupting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) nop nop nop nop write di a-b pre di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t wr is referenced from the first positive ck edge after the last data in pair. a10 is low with the write comm and (auto prechar ge is disabled). ck ck command address dqs dq dm don?t care ba a, col b ba (a or all) t wr maximum dqss t1 t2 t3 t4 t5 t6 nop nop nop nop write pre ck ck command address ba a, col b ba (a or all) t wr minimum dqss di a-b dqs dq dm t dqss (min) t rp t rp
data sheet 41 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 26 write to precharge: interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address maximum dqss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) minimum dqss t wr t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t wr 3 = these bits are incorrectly written into the memory array if dm is low. 3 3 3 3
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 42 rev. 1.0, 2004-03 figure 27 write to precharge: minimum dqss, odd number of data (1-bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t wr t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written into the memory array if dm is low. 4 = these bits are incorrectly written into the memory array if dm is low.
data sheet 43 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description figure 28 write to precharge: nominal dqss (2-bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t wr is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the write command (auto precharge is disabled). 1 = can be don't care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don't care at this point. don?t care t1 t2 t3 t4 t5 t6 nop nop nop pre write nop ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t wr 3 3 3 = these bits are incorrectly written into the memory array if dm is low.
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 44 rev. 1.0, 2004-03 3.5.4 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 29 precharge command ba high ba = bank address ck ck cke cs ras cas we a10 ba0, ba1 don?t care all banks one bank (if a10 is low, otherwise don?t care). a0-a9, a11, a12
data sheet 45 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 3.5.5 power-down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power-down. in that case, the dll must be enabled after exiting power-down, and 200 clock cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. however, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command may be applied one clock cycle later. figure 30 power down t is t is ck ck cke command no column access in progress valid nop valid don?t care exit power down mode enter power down mode (burst read or write operation must not be in progress) nop
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 46 rev. 1.0, 2004-03 1. cken is the logic state of cke at clock edge n: cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. table 7 truth table 2: clock enable (cke) current state cke n-1 cken command n action n notes previous cycle current cycle self refresh l l x maintain self-refresh ? self refresh l h deselect or nop exit self-refresh 1) power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or nop precharge power-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? hhsee table 8 ?? 1) deselect or nop commands should be issued on any clock edges occurring during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. table 8 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation. 1)2)3)4)5)6) 1) this table applies when cke n-1 was high and cke n is high (see table 7 and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. l h h h no operation nop. continue previous operation. 1) to 6) idle l l h h active select and activate row 1) to 6) lllhauto refresh? 1) to 7) llllmode register set ? 1) to 7) row active l h l h read select column and start read burst 1) to 6), 8) l h l l write select column and start write burst 1) to 6), 8) l l h l precharge deactivate row in bank(s) 1) to 6), 9) read (auto precharge disabled) l h l h read select column and start new read burst 1) to 6), 8) l l h l precharge truncate read burst, start precharge 1) to 6), 9) l h h l burst terminate burst terminate 1) to 6), 10) write (auto precharge disabled) l h l h read select column and start read burst 1) to 6), 8), 11) l h l l write select column and start write burst 1) to 6), 8) l l h l precharge truncate write burst, start precharge 1) to 6), 9), 11)
data sheet 47 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to table 9 . 5) the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle. 8) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 9) may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 10) not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 11) requires appropriate dm masking.
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 48 rev. 1.0, 2004-03 table 9 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action notes any h x x x deselect nop. continue previous operation. 1)2)3)4)5)6) l h h h no operation nop. continue previous operation. 1) to 6) idle xxxxany command otherwise allowed to bank m ? 1) to 6) row activating, active, or precharging l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7) l h l l write select column and start write burst 1) to 7) l l h l precharge ? 1) to 6) read (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7) l l h l precharge ? 1) to 6) write (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 8) l h l l write select column and start new write burst 1) to 7) l l h l precharge ? 1) to 6) read (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7), 9) l h l l write select column and start write burst 1) to 7), 9), 10) l l h l precharge ? 1) to 6) write (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7), 9) l h l l write select column and start new write burst 1) to 7), 9) l l h l precharge ? 1) to 6) 1) this table applies when cke n-1 was high and cke n is high (see table 7 : clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see 10) . write with auto precharge enabled: see 10) . 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved.
data sheet 49 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] functional description 7) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dm masking. 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 10 . 10) a write command may be applied after the completion of data output. table 10 truth table 5: concurrent auto precharge from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck
hyb25d512[16/40/80]0at?[6/7/7f] functional description data sheet 50 rev. 1.0, 2004-03 3.6 simplified state diagram figure 31 simplified state diagram self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a burst stop preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge
data sheet 51 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics 4 electrical characteristics 4.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 11 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq +0.5 v ? voltage on inputs relative to v ss v in ?1.0 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1.0 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1.0 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1.5? w? short circuit output current i out ?50? ma? table 12 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 1.5 ? 2.5 pf tsopii 1) 1) these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 100 mhz, t a = 25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. delta input capacitance c di1 ??0.25pf 1) input capacitance: all other input-only pins c i2 2.0 ? 3.0 pf tsopii 1) delta input capacitance: all other input-only pins c dio ??0.5pf 1) input/output capacitance: dq, dqs, dm c io 4.0 ? 5.0 pf tsopii 1)2) 2) dm inputs are grouped with i/o pins reflecting the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level. delta input/output capacitance: dq, dqs, dm c dio ??0.5pf 1)
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 52 rev. 1.0, 2004-03 4.2 normal strength pull-down a nd pull-up characteristics 1. the nominal pull-down v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the full variation in driver pull-down current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 3. the nominal pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 4. the full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 5. the full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 32 normal strength pull-down characteristics figure 33 normal strength pull-up characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 i out (ma) v ddq - v out (v) maximum nominal high nominal low minimum maximum nominal high nominal low minimum v ddq - v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 i out (ma)
data sheet 53 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics table 13 normal strength pull-down and pull-up currents voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 table 14 pull-down and pull-up process variations and conditions parameter nominal minimum maximum operating temperature 25 c0 c 70 c v dd / v ddq 2.5 v 2.3 v 2.7 v
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 54 rev. 1.0, 2004-03 4.3 weak strength pull-down a nd pull-up characteristics 1. the weak pull-down v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 2. the weak pull-up v - i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v - i curve. 3. the full variation in driver pull-up current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v - i curve. 4. the full variation in the ratio of the maximum to minimum pull-up and pull-down current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain to source voltages from 0.1 to 1.0 v. figure 34 weak strength pull-down characteristics figure 35 weak strength pull-up characteristics 0 10 20 30 40 50 60 70 80 0,0 0,5 1,0 1,5 2,0 2,5 vout [v] iout [ma] maxim um typical high typical low minim um -80,0 -70,0 -60,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0 0,0 0,5 1,0 1,5 2,0 2,5 vout [v] iout [v] maximum typical high typical low minimum
data sheet 55 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics table 15 weak strength driver pull-down and pull-up characteristics voltage (v) pulldown current (ma) pullup current (ma) nominal low nominal high min. max. nominal low nominal high min. max. 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 56 rev. 1.0, 2004-03 4.4 ac characteristics (notes 1-5 apply to the following tables; electrical characteristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electrical characteristics and ac timing.) notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. figure 36 represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/fall derating, ddr sdram slew rate standards, overshoot & undershoot specification and clamp v - i characteristics see the latest jedec specification for ddr components. figure 36 ac output load circuit diagram / timing reference load 50 ? timing reference point output ( v out ) 30 pf v tt
data sheet 57 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics table 16 ac operating conditions 1) parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 ? v 2)3) input low (logic 0) voltage, dq, dqs and dm signals v il(ac) ? v ref - 0.31 v 2)3) input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 2)3)4) input closing point voltage, ck and ck inputs v ix(ac) 0.5 v ddq - 0.2 0.5 v ddq + 0.2 v 2)3)5) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. 4) v id is the magnitude of the difference between the input level on ck and the input level on ck . 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. table 17 ac timing - absolute specifications ddr333, ddr266a and ddr266 tsop parameter symbol ?6 ?7 ?7f unit note/ test condition 1) ddr333 ddr266a ddr266 min. max. min. max. min. max. dq output access time from ck/ck t ac ?0.7 +0.7 ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck3 ?? t ck2.5 6.0 12 7.5 12 7.5 12 ns cl = 2.5 2)3)4)5) t ck2 7.5 12 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.45 ? 0.5 ? 0.5 ? ns 2)3)4)5) dq and dm input setup time t ds 0.45 ? 0.5 ? 0.5 ? ns 2)3)4)5) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.7 +0.7 ?0.75 ? ?0.75 +0.75 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.75 +0.75 ?0.75 +0.75 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck 2)3)4)5)
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 58 rev. 1.0, 2004-03 dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.45 ? +0.5 ? +0.5 ns tsop 2)3)4)5) data hold skew factor t qhs ? +0.55 ? +0.75 ? +0.75 ns tsop 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs t hp ? t qhs ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2? 2? 2? t ck 2)3)4)5) write preamble setup time t wpres 0? 0? 0? ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.75 ? 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 1.0 ? 1.0 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.75 ? 0.9 ? 0.9 ? ns fast slew rate 3)4)5)6)10) 0.8 ? 1.0 ? 1.0 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 42 70e+3 45 120e+3 45 120e+3 ns 2)3)4)5) active to active/auto- refresh command period t rc 60 ? 65 ? 65 ? ns 2)3)4)5) auto-refresh to active/auto-refresh command period t rfc 72 ? 75 ? 75 ? ns 2)3)4)5) active to read or write delay t rcd 18 ? 20 ? 20 ? ns 2)3)4)5) precharge command period t rp 18 ? 20 ? 20 ? ns 2)3)4)5) active to autoprecharge delay t rap t rcd or t rasmin t rcd or t rasmin t rcd or t rasmin ns 2)3)4)5) active bank a to active bank b command t rrd 12 ? 15 ? 15 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck ) + ( t rp / t ck ) t ck 2)3)4)5)11) table 17 ac timing - absolute specifications ddr333, ddr266a and ddr266 tsop parameter symbol ?6 ?7 ?7f unit note/ test condition 1) ddr333 ddr266a ddr266 min. max. min. max. min. max.
data sheet 59 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics internal write to read command delay t wtr 1? 1? 1? t ck 2)3)4)5) exit self-refresh to non- read command t xsnr 75 ? 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 ? 7.8 s 2)3)4)5)12) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v 2) input slew rate 1 v/ns for ddr266a 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 17 ac timing - absolute specifications ddr333, ddr266a and ddr266 tsop parameter symbol ?6 ?7 ?7f unit note/ test condition 1) ddr333 ddr266a ddr266 min. max. min. max. min. max.
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 60 rev. 1.0, 2004-03 table 18 i dd conditions parameter symbol operating current: one bank; active/ precharge; t rc = t rcmin ; t ck = t ckmin ; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current: one bank; active/read/precharge; burst = 4; refer to the following page for detailed test conditions. i dd1 precharge power-down standby current: all banks idle; power-down mode; cke v ilmax ; t ck = t ckmin i dd2p precharge floating standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs changing once per clock cycle, v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs stable at v ihmin or v ilmax ; v in = v ref for dq, dqs and dm. i dd2q active power-down standby current: one bank active; power-down mode; cke v ilmax ; t ck = t ckmin ; v in = v ref for dq, dqs and dm. i dd3p active standby current: one bank active; cs v ihmin ; cke v ihmin ; t rc = t rasmax ; t ck = t ckmin ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current: one bank active; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin ; i out =0ma i dd4r operating current: one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin i dd4w auto-refresh current: t rc = t rfcmin , burst refresh i dd5 self-refresh current: cke 0.2 v; external clock on; t ck = t ckmin i dd6 operating current: four bank; four bank interleaving with bl = 4; refer to the following page for detailed test conditions. i dd7
data sheet 61 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics table 19 i dd specification and conditions symbol ?6 ?7 ?7f unit note/test condition 1) 1) test conditions for typical values: v dd = 2.5 v (ddr266, ddr333), t a = 25 c, test conditions for maximum values: v dd = 2.7 v, t a = 10 c ddr333 ddr266a ddr266 typ. max. typ. max. typ. max. i dd0 155 200 135 170 147 185 ma x4/x8 2)3) 2) i dd specifications are tested after the device is properly initialized and measured at 133 mhz for ddr266, 166 mhz for ddr333. 3) input slew rate = 1 v/ns. 155 200 135 170 140 177 ma x16 3) i dd1 170 215 145 180 158 196 ma x4/x8 3) 170 215 145 180 151 187 ma x16 3) i dd2p 12 18 10 14 10 14 ma 3) i dd2f 45 60 40 50 40 50 ma 3) i dd2q 30 40 20 28 20 28 ma 3) i dd3p 17 23 14 18 14 18 ma 3) i dd3n 60 75 55 70 55 70 ma x4/x8 3) 60 75 55 70 55 70 ma x16 3) i dd4r 200 245 165 200 172 208 ma x4/x8 3) 200 245 165 200 172 208 ma x16 3) i dd4w 190 235 160 195 166 203 ma x4/x8 3) 110 130 90 105 94 109 ma x16 3) i dd5 270 335 255 310 270 329 ma 3)4) 4) enables on-chip refresh and address counters. i dd6 2.5 5 2.5 5 2.5 5 ma x4/x8 3) i dd7 330 405 315 380 331 399 ma x4/x8 3) 330 405 315 380 343 414 ma x16 3)
hyb25d512[16/40/80]0at?[6/7/7f] electrical characteristics data sheet 62 rev. 1.0, 2004-03 4.5 i dd1 : operating current: one bank operation 1. only one bank is accessed with t rcmin . burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0 ma. 2. timing patterns a) ddr200 (100 mhz, cl = 2): t ck = 10 ns, cl = 2, bl = 4, t rcd = 2 t ck , t ras = 5 t ck setup: a0 n r0 n n p0 n read: a0 n r0 n n p0 n - repeat the same timing with random address changing 50% of data changing at every burst b) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, cl = 2, bl = 4, t rcd = 3 t ck , t rc = 9 t ck , t ras = 5 t ck setup: a0 n n r0 n p0 n n n read: a0 n n r0 n p0 n nn - repeat the same timing with random address changing 50% of data changing at every burst c) ddr333 (166 mhz, cl = 2.5): t ck = 6 ns, cl = 2.5, bl = 4, t rcd = 3 t ck , t rc = 9 t ck , t ras = 5 t ck setup: a0 n n r0 n p0 n n n read: a0 n n r0 n p0 n n n - repeat the same timing with random address changing 50% of data changing at every burst 3. legend: a = activate, r = read, w = write, p = precharge, n = nop i dd7 : operating current: four bank operation 1. four banks are being interleaved with t rcmin . burst mode, address and control inputs on nop edge are not changing. i out = 0 ma. 2. timing patterns a) ddr200 (100 mhz, cl = 2): t ck = 10 ns, cl = 2, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck , read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 read: a0 r3 a1 r0 a2 r1 a3 r2 - repeat the same timing with random address changing 50% of data changing at every burst b) ddr266a (133 mhz, cl = 2): t ck = 7.5 ns, cl = 2, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read: a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst c) ddr333 (166 mhz, cl = 2.5): t ck = 6 ns, cl = 2.5, bl = 4, t rrd = 2 t ck , t rcd = 3 t ck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read: a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every burst 3. legend: a = activate, r = read, w = write, p = precharge, n = nop
data sheet 63 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams 5 timing diagrams figure 37 data input (write), timing burst length = 4 figure 38 data output (read), timing burst length = 4 t dh t ds t dh t ds t dqsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don?t care t dqsh t qh (data output hold time from dqs) t dqsq and t qh are only shown once and are shown referenced to diff erent edges of dqs, only for clarify of illustration. . dqs dq t dqsq max t qh t dqsq and t qh both apply to each of the four relevant edges of dqs. t dqsq max. is used to determine the worst case setup time for controller data capture. t qh is used to determine the worst case hold time for controller data capture.
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 64 rev. 1.0, 2004-03 figure 39 initialize and mode register sets t ih 200 s t is t ih t is t ih t is t ih t is t ih t is t ih t is t ih t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t ch t vtd pre emrs mrs pre ar ar mrs nop act code code code ra code code code ra ba0=l ba0=l ba high-z high-z power-up: vdd and ck stable extended mode register set load mode register, reset dll load mode register (with a8 = l) vdd vddq vtt (system * ) vref ck cke command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos low level all banks ba0=h ba1=l ba1=l ba1=l all banks * vtt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to zero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don?t care 200 cycles of ck ** ck
data sheet 65 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams figure 40 power down mode t ih t is t ih t is t is t is t ih t is t cl t ch t ck nop valid valid * valid valid enter power down mode exit power down mode no column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an active (or if at least one row is already active), then the power down mode shown is active power down. cke command addr dqs dq dm don?t care c k c k nop
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 66 rev. 1.0, 2004-03 figure 41 auto refresh mode t ih t is t ih t is t ih t is t rfc t rp t cl t ch t ck pre nop nop ar nop ar nop nop nop ra ra ba pre = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. nop commands are shown for ease of illustration; other valid commands may be possible at these times. dm, dq, and dqs signals are all don't care/high-z for operations shown. valid valid act ra cke command a0-a8 a9, a11,a12 a10 ba0, ba1 dqs dq dm bank(s) don?t care all banks one bank t rfc ck ck
data sheet 67 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams figure 42 self refresh mode 200 cycles t ih t is t xsrd, t xsrn t ih t is t is t is t ih t is t rp * t ck t cl t ch ar valid nop valid enter self refresh mode exit self refresh mode nop * = device must be in the all banks idle state before entering self refresh mode. ** = t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck). cke command addr dqs dq dm don?t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 68 rev. 1.0, 2004-03 figure 43 read without auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck pre nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid nop read col n ra ra ba x * do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all banks one bank t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n c k c k dis ap dis ap = disable auto precharge.
data sheet 69 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams figure 44 read with auto precharge (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t ih t is t rp t cl t ch t ck nop nop nop act nop nop nop nop do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. nop commands are shown for ease of illustration; other commands may be valid at these times. ba x valid valid valid nop read col n ra ra do n cke command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpre cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n en ap ba x c k c k t lz (min)
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 70 rev. 1.0, 2004-03 figure 45 bank read access (burst length = 4) t hz (max) t lz (max) t hz (min) t rpst t lz (min) t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck read nop pre nop nop act nop nop ba x ba x* valid nop act ra ra ba x do n c k c k cke command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpre cl=2 cl=2 t rpre don?t care case 1: t ac /t dqsck = min case 2: t ac /t dqsck = max t rpst t ac (max) t lz (max) t dqsck (min) t ac (min) do n col n ra ra all banks ra one bank dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t lz (min)
data sheet 71 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams figure 46 write without auto precharge (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t rp t cl t ch t ck nop nop nop pre nop nop act nop ba x ba nop write col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din c k c k cke command a10 ba0, ba1 dqs dq dm dis ap all banks one bank t wr t wpres t dqsh don?t care a0-a9, a11, a12 t dqss = min. t dqss t wpre t dsh
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 72 rev. 1.0, 2004-03 figure 47 write with auto precharge (burst length = 4) nop commands are shown for ease of illustration; other valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t ih t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop nop nop nop act nop ba x ba nop write col n ra ra valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = enable auto precharge. c k c k cke command a10 ba0, ba1 dqs dq dm t wr t dqss t wpres t dqsh don?t care valid valid en ap a0-a9, a11, a12 t dal t dqss = min. t dsh t wpre din
data sheet 73 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams figure 48 bank write access (burst length = 4) t wpst t dqsl t ih t is t ih t is t ih t is t ih t is t ih t is t cl t ch t ck t ras write nop nop nop nop pre nop nop ba x nop act ra ra di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n. dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. din valid ba x cke command a10 ba0, ba1 dqs dq dm ck ck t wpres t wr t rcd all banks one bank dis ap don?t care a0-a9, a11, a12 col n ba x t dqss t dqsh t dsh t wpre t dqss = min.
hyb25d512[16/40/80]0at?[6/7/7f] timing diagrams data sheet 74 rev. 1.0, 2004-03 figure 49 write dm operation (burst length = 4) t ih t wpst t dqsl t ih t is t ih t is t is t rp t cl t ch t ck nop nop nop pre nop nop act nop nop write col n ra din ck ck cke command a10 ba0, ba1 dqs dq dm t wr t dqss don?t care valid t ih t is t ih t is ba x ba ra ba x * all banks one bank dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * = don't care if a10 is high at this point. pre = precharge; act = active; ra = row address; ba = bank address. nop commands are shown for ease of illustration; other valid commands may be possible at these times. a0-a9, a11, a12 t dqsh t dsh t dqss = min. t wpres
data sheet 75 rev. 1.0, 2004-03 hyb25d512[16/40/80]0at?[6/7/7f] package outlines 6 package outlines figure 50 p-tsop66ii-1 (plastic thin small outline package type ii) 1) does not include plastic or metal protrusion of 0.15 max. per side 2) does not include plastic protrusion of 0.25 max. per side 3) does not include dambar protrusion of 0.13 max. 0.12 33 1 index marking 2.5 max. 22.22 1) 0.13 0.3 0.65 3) 6 max. 0.08 66 0.65 32 x 34 15? 15? 20.8 = 5? 5? 0.05 0.1 10.16 66x m 66x 0.1 0.05 1 0.25 2) 11.76 0.5 0.2 0.1 0.13 +0.06 -0.03 0.15 smd = surface mounted device you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
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